For more than three decades, the continued miniaturization of silicon-based metal oxide semiconductor field effect transistors (MOSFETs) has driven the worldwide semiconductor industry. Various impediments to continued scaling have been predicted for decades, but a history of innovation has sustained Moore's Law in spite of many challenges. Recently, however, there have been indications that Si-based metal oxide semiconductor transistors are beginning to reach their traditional scaling limits. A concise summary of near-term and long-term challenges to continued complementary metal oxide semiconductor (CMOS) scaling can be found in the “Grand Challenges” section of the 2002 Update of the International Technology Roadmap for Semiconductors (ITRS). A very thorough review of the device, material, circuit, and systems can be found in Proc. IEEE, Vol. 89, No. 3, March 2001, a special issue dedicated to the limits of semiconductor technology.
Since it has become increasingly difficult to improve MOSFETs and therefore CMOS performance through continued scaling, methods for improving performance without scaling have become critical. One approach for doing this is to increase carrier (electron and/or hole) mobilities. For example, there are ongoing efforts to increase the performance of CMOS devices by altering the material used to form the conduction channel in such a way that charge carrier transport is increased in comparison with conventional Si-based semiconductors. Ge has carrier mobility that is significantly higher than that of Si and therefore has been the subject of renewed interest in the CMOS community. Ge layers under compressive strain have an even higher charge carrier mobility than that of unstrained Ge. Bulk Ge wafers are becoming available, but a Ge-on-insulator (GeOI) material as well as a bulk substrate including a surface region comprising Ge have proven to be far more difficult to fabricate. Additionally, due to the large lattice mismatch between Ge and Si (4.17%), it is difficult to grow strained Ge surface layers that remain both planar (smooth) and stable against the generation of strain-relieving dislocations.
In view of the state of the art mentioned above, there is a need for providing a method of fabricating a Ge-containing substrate material in which a Ge rich region is located at or near a surface of a semiconductor substrate, in a strained state, resistant to plastic relaxation and existing over a buried insulating layer. Ge-containing substrate material including the surface Ge rich region can be used as a substrate in which CMOS devices, such as FETs, can be fabricated thereon.